The invention lies in the field of integrated circuits. The invention relates to a nonvolatile flash memory cell that can be written to and erased electrically and has the form of a semiconductor oxide nitride oxide semiconductor (SONOS) cell. The invention also relates to an associated production method.
One aim in the development of memory modules is to specify a memory cell configuration that is as small as possible, but which nevertheless allows rapid random access to individual memory locations. If possible, it should be possible to produce such a memory cell configuration using conventional production technologies, in particular, for the electronic components provided in the drive periphery.
Very small nonvolatile memory cells are required for very large scale integration densities in multimedia applications. Until now, floating gate flash cells using a NAND, AND, or virtual ground NOR architecture have mainly been used, with the smallest memory cells known from products having an area of 5F2. The virtual ground configuration, however, does not allow rapid random read access, which requires a low impedance of its (metallic) bit line as far as the individual memory cell. Standard T-shaped cells with a metallic connection require a considerably larger cell area due to the adjustment separations that are required; floating gate cells such as these whose area is 12F2 are now normal.
The publication xe2x80x9cAnalysis of Carrier Traps in Si3N4 in Oxide/Nitride/Oxide for Metal/Oxide/Nitride/Oxide/Silicon Nonvolatile Memoryxe2x80x9d by H. Aozasa et al., in Jpn. J. Appl. Phys. 38, 1441-1447 (1999) describes and investigates a memory layer structure based on an oxide-nitride-oxide layer sequence.
U.S. Pat. No. 5,397,726 to Bergemont describes a flash EPROM in which the memory layer structure is disposed between the semiconductor body and the gate electrode, the source line is provided as a common source connection for a number of memory cells, and a floating gate electrode is provided as the memory layer.
U.S. Pat. No. 6,080,624 to Kamiya et al. describes a nonvolatile semiconductor memory in which a floating gate electrode, provided as a memory layer, is disposed between a gate dielectric and an ONO layer.
U.S. Pat. No. 5,918,124 to Sung discloses the formation of spacing elements for lightly doped drain (LDD) source/drain regions in a multiple memory EEPROM cell.
It is accordingly an object of the invention to provide a memory cell and production method that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that provides a nonvolatile memory cell for a very large scale integration density, with short access times, and an associated production method.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a memory cell disposed on a semiconductor body having a top face, the memory cell including a source region formed at the top face, a drain region, a gate line, a gate electrode disposed between the source region and the drain region at the top face, the gate electrode being part of the gate line, the gate line structured in strips and being a word line, a source line being a common source connection for a plurality of memory cells, the source line electrically contacting the source region between the gate electrode and another gate electrode of another of the plurality of memory cells, a drain line being a metallic interconnect electrically conductively connected to the drain region and disposed as a bit line running transversely with respect to the gate line and electrically isolated from the gate line, supply leads respectively connected to the source line, the drain line, and the gate line, and a memory layer structure having a first boundary layer, a second boundary layer, and a memory layer disposed in between the first boundary layer and the second boundary layer. The memory layer, the first boundary layer, and the second boundary layer are each made from a material having a respective energy band gap. The material of the memory layer has a relatively narrow energy band gap. The material of the first boundary layer and the second boundary layer has a relatively wide energy band gap. The memory layer structure is disposed between the semiconductor body and the gate electrode.
In other words, the memory cell according to the invention has an ONO layer structure or an equivalent memory layer structure between a gate electrode and the channel region formed in the semiconductor body. The gate electrode is a component of a word line in strip form. There are source and drain regions between the gate electrodes of adjacent memory cells. The source regions are provided with polysilicon layers that are in strip form and are connected between the gate electrodes to provide common source lines. The drain regions are connected through polysilicon fillings to metallic interconnects that are applied to the top face as bit lines. In the transverse direction with respect to the sequence of the source region, gate electrode, and drain region, the individual cells in a memory cell configuration are isolated from one another by narrow isolation trenches (STI, shallow trench isolation). A preferred production method is particularly suitable for integration in a production process by which the electronic drive components in the periphery of the memory are also produced together with the memory cell configuration.
In accordance with another feature of the invention, there are provided isolation trenches in the semiconductor body separating the memory cell in the semiconductor body from further memory cells disposed on both sides of the memory cell in a direction of the gate line.
In accordance with a further feature of the invention, the source region and the drain region each have two sides, a gate electrode is disposed on each of the two sides of the source region and the drain region, the source line is a conductively doped polysilicon layer shaped as a strip and fills a region between the gate electrodes above the source region, a further conductively doped polysilicon layer is shaped as a strip and fills a region between the gate electrodes above the drain region and contacts the metallic drain line, and electrically isolating parting layers are respectively disposed between the gate electrodes and the polysilicon layer and the further polysilicon layer.
In accordance with an added feature of the invention, only one gate electrode is disposed in the memory cell between the polysilicon layer above the source region and the further polysilicon layer above the drain region.
In accordance with an additional feature of the invention, the gate electrode and a further gate electrode, provided as a select-gate electrode, of another memory cell of the plurality of memory cells are disposed in series through a further source region and further drain region of the other memory cell, and the gate electrode and the further gate electrode are disposed between the polysilicon layer above the source region and the further polysilicon layer above the drain region.
In accordance with yet another feature of the invention, the source region and the drain region each have a given dopant concentration, and a lightly doped drain region has a dopant concentration less than the dopant concentration in the source region and in the drain region, the lightly doped drain region is connected to the source region and to the drain region in a direction toward a respectively adjacent gate electrode in another of the plurality of memory cells.
In accordance with yet a further feature of the invention, the memory layer is silicon nitride, and the first boundary layer and second boundary layer are silicon oxide. Alternatively, the memory layer is tantalum oxide or hafnium silicate, and the first boundary layer and second boundary layer are silicon oxide. The memory layer can include hafnium oxide, hafnium silicate, zirconium oxide, or zirconium silicate, and the first boundary layer and the second boundary layer are aluminum oxide or silicon oxide containing aluminum.
The actual memory layer is disposed between boundary layers in the memory layer structure and is embedded in material having a wider energy band gap such that the charge carriers that are respectively received in the memory layer through the source region and through the drain region remain localized there. One preferable material for the memory layer is a nitride; an oxide is particularly suitable for the surrounding material. In a memory cell using silicon in the material system, the memory cell in the example is silicon nitride with an energy band gap of about 5 eV, and the surrounding boundary layers are silicon oxide with an energy band gap of about 9 eV. The memory layer may be a different material with a smaller energy band gap than that of the boundary layers, in which case, the difference between the energy band gaps is intended to be as great as possible to achieve good electrical confinement of the charge carriers. Thus, for example, tantalum oxide, hafnium silicate, or intrinsically conductive (undoped) silicon may be used, in conjunction with silicon oxide, as the material for the memory layer. In preferred embodiments, the memory layer may also, specifically, contain hafnium oxide, hafnium silicate, zirconium oxide, or zirconium silicate, and the boundary layers may be aluminum oxide or silicon oxide containing aluminum. Silicon nitride has a relative dielectric constant of about 7.9. The use of an alternative material having a higher dielectric constant (for example approximately 15 . . . 18) allows the total thickness of the layer stack provided for storage to be reduced, and is, thus, advantageous.
In accordance with yet an added feature of the invention, the gate electrode is formed by a conductively doped polysilicon layer and a layer containing metal and/or a layer sequence containing metal applied to the conductively doped polysilicon layer.
In accordance with yet an additional feature of the invention, the layer containing metal is a metal silicide or a double layer made of a metal nitride and a pure metal layer. Particularly, the layer containing metal is tungsten silicide or a double layer made of tungsten nitride and tungsten.
In accordance with again another feature of the invention, the first boundary layer is an oxide layer and is between 2.5 nm to 8 nm thick, the second boundary layer is an oxide layer and is between 3 nm to 12 nm thick, and the memory layer is between 1 nm to 5 nm thick.
In accordance with again a further feature of the invention, the drain line is a layer sequence made of titanium, titanium nitride, and tungsten or tantalum, tantalum nitride, and copper, in a direction of increasing distance from the drain region.
With the objects of the invention in view, there is also provided a method for producing a memory cell configuration, including the steps of producing a number of strip-shaped isolation trenches running in a straight line in parallel at a distance from one another in a semiconductor body, the semiconductor body having a given doping, applying a layer sequence including a first boundary layer, a memory layer, a second boundary layer, the first boundary layer, the memory layer, and the second boundary layer each made of a material having a respective energy band gap, the memory layer having a relatively narrow energy band gap and the first and second boundary layers having a relatively wide energy band gap, a conductively doped polysilicon layer, at least one layer containing metal, and a nitride layer, structuring the layer sequence into strip elements at least as far as the memory layer, the strip elements running in a straight line in parallel at a distance from one another transversely with respect to the isolation trenches, applying a further nitride layer to substantially all of a top surface of the strip elements, implanting a dopant to form lightly doped drain regions between the strip elements, producing spacing elements on sides of the strip elements, implanting dopant to form source and drain regions in regions between the spacing elements, filling spaces between the strip elements with electrically insulating material, substantially removing the insulating material in regions intended for a connection of the source and drain regions using a mask, with the insulating material remaining between the respective drain regions above the isolation trenches, removing the further nitride layer in open regions between the spacing elements and removing the spacing elements, filling the regions from which the insulating material was removed with an electrically conductively doped polysilicon layer, producing a dielectric layer outside regions of the polysilicon layer disposed above the drain region, and applying metallic drain lines and structuring the drain lines into strips disposed transversely with respect to the strip elements to respectively electrically conductively connect each of the drain lines to respective drain regions following one another in a straight line and to the polysilicon layer.
In accordance with again an added mode of the invention, the substantially removing the insulating material step is performed by leaving insulating material between an even-numbered strip element and a subsequent odd-numbered strip element, with respect to a sequential numbering of the strip elements, to form insulated source/drain regions between a respective drive gate and a select gate.
In accordance with again an additional mode of the invention, the insulating material between two components of the strip elements and between which there are source regions intended for connection to the polysilicon layer is completely removed to form source lines each electrically conductively connected to respective source regions following one another in a straight line.
In accordance with still another mode of the invention, the at least one layer containing metal is a metal silicide or a double layer made of a metal nitride and a pure metal layer.
In accordance with still a further mode of the invention, the at least one layer containing metal is tungsten silicide or a double layer made of tungsten nitride and tungsten.
In accordance with still an added mode of the invention, the substantially removing the insulating material step is performed before the removing the further nitride layer step.
In accordance with a concomitant mode of the invention, the removing the further nitride layer step is performed before the substantially removing the insulating material step.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory cell and production method, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.